Inter-Module Interconnect Strategy for System on Chip Applications

Interconnect effects that negatively impact performance, and compromise signal integrity are becoming more pronounced as technology moves deeper into sub-micron feature sizes, and designs are operated at higher frequencies. Many interconnect configurations and techniques have been proposed for a variety of domains (FPGA’s, ASIC’s, and networks...). In this work, we begin by investigating these techniques as they apply to the System on Chip (SoC) application domain. In particular, we restrict our analysis to an envisioned future embedded system architecture that consists of an interconnection of hundreds to thousands of 50K-100K gate IP (Intellectual Property) blocks. We assume that today’s design, placement, routing, and interconnect optimization methods can handle intra-block problems, and the main issue to address is inter-module interconnection. Our work culminates in the proposal and evaluation, with respect to area/performance/power, of a new interconnect strategy engineered specifically for the IP “plug-and-play” SoC domain.